Advance Packaging Technology
Moore’s Law is no longer cost-efficient due to challenges of lithography processes and tools. The industry is now diligently using advanced packaging technologies to put multiple advanced and/or mature chips in a single package, which is also known as heterogeneous integration. Together with 3D packaging this extends Moore’s Law at system-level.
We are offering alternatives to design and manufacturing of the latest Systems-on-Chips (SoCs), using System-in-Package (SiP) and chiplet-based approaches by leveraging our Advanced Packaging Technology to mix both the latest and mature nodes. 2.5D/3D packaging is accelerating into new technical breakthroughs for 3D Interconnect Density.
Hybrid bonding is gaining momentum as it races to be the new permanent bonding method in 3D device stacking. GSME’s cutting-edge advanced-technology packaging solutions enable customers to maximize power and performance of their chips while still meeting the strict size requirements of today’s new system applications. The technology produces devices that have significantly high-density interconnects. 2.5D-3D stacking has been achieved using ‘through silicon via’ (TSV) technology for its high electrical performance.
Our cost-effective technology offerings of advanced packaging and hybrid bonding could outweigh limitations this industry is experiencing due to slowdown of Moore’s law.
BGA Package
A BGA (Ball Grid Array) package is a surface-mount (chip carrier) package that provides more interconnection pins than dual in-line or flat packaging because the whole surface can be used, rather than just the perimeter. The advantages are that BGA packaging enables high density for small designs, has a lower thermal resistance to prevent overheating, and features low inductance leads for optimal electrical performance.
BGA Package
A BGA (Ball Grid Array) package is a surface-mount (chip carrier) package that provides more interconnection pins than dual in-line or flat packaging because the whole surface can be used, rather than just the perimeter. The advantages are that BGA packaging enables high density for small designs, has a lower thermal resistance to prevent overheating, and features low inductance leads for optimal electrical performance.
Flip Chip BGA Package
A Flip Chip BGA (Ball Grid Array) package features a controlled collapse chip connection (flip chip) die-to-substrate interconnection. This offers greater design flexibility with higher signal density and functionality, all in a small footprint. The advantages of Flip Chip BGA packaging over wire-bond BGA packages is that the die/package interface can be located near the chip subsystem on the die, which results in optimal power and signal integrity.
Wafer Bumping
Wafer Bumping technology forms metal solder balls, or bumps, on the wafer prior to dicing. This technology results in optimal electrical performance, higher current carrying capacity, a small footprint and lower cost.
Wafer Bumping
Wafer Bumping technology forms metal solder balls, or bumps, on the wafer prior to dicing. This technology results in optimal electrical performance, higher current carrying capacity, a small footprint and lower cost.
Copper (Cu) Pillars
Copper pillar offers a finer pitch alternative to solder bumps to form interconnects between the chip and the package substrate, interposer, or other chips in 3D integration. It is an ideal solution for applications where fine pitch, ROHS/Green compliance, low cost and electromigration performance is required.
WLCSP Package
A Wafer Level Chip-Scale Package (WLCSP) is true chip-scale solution since the package is the same size as the die. With this technology, the packaging of an IC takes place at the wafer-level, rather than the traditional practice of creating individual packaged units after dicing them from a wafer. The advantage of WLCSP is that the die-to-PCB inductance is reduced, resulting in a smaller package size and enhanced thermal conduction.
WLCSP Package
A Wafer Level Chip-Scale Package (WLCSP) is true chip-scale solution since the package is the same size as the die. With this technology, the packaging of an IC takes place at the wafer-level, rather than the traditional practice of creating individual packaged units after dicing them from a wafer. The advantage of WLCSP is that the die-to-PCB inductance is reduced, resulting in a smaller package size and enhanced thermal conduction.
FOWLP Package
A Fan-out Wafer Level Package features connections that are fanned out of the chip surface, which enables more external I/Os. The interposer is built directly on top of the die and is essentially a true chip-scale packaging technology since the package is roughly the same size as the die. However, this technology allows for the distribution of I/Os beyond the die surface, which supports a thinner package and allows for more I/Os than other package technologies. This substrate-less package features lower thermal resistance and high performance. Its System in Package (SiP) architecture enables multiple dies and components to be combined in a small footprint.
FIWLP Package
A Fan-in Wafer Level Package is a true chip-scale technology because the resulting package is the same size as the die. The interposer is built directly on top of the die. It is ideal for cost and space-constrained mobile devices and new applications such as wearables and automotive electronics.
FIWLP Package
A Fan-in Wafer Level Package is a true chip-scale technology because the resulting package is the same size as the die. The interposer is built directly on top of the die. It is ideal for cost and space-constrained mobile devices and new applications such as wearables and automotive electronics.
Advanced QFN Package
A QFN (Quad Flat No-lead) packaging is a low cost, small form factor (near chip scale), light-weight solution featuring excellent thermal and electrical performance and reduced lead inductance. It’s deal for applications where size, weight and thermal and electrical performance are important.
Advanced PCB & Substrate Technology
